// +FHDR------------------------------------------------------------
//                 Copyright (c) 2022 .
//                       ALL RIGHTS RESERVED
// -----------------------------------------------------------------
// Filename      : cpu_transaction.sv
// Author        : 
// Created On    : 2022-08-25 14:42
// Last Modified : 
// -----------------------------------------------------------------
// Description:
//
//
// -FHDR------------------------------------------------------------

`ifndef __CPU_TRANSACTION_SV__
`define __CPU_TRANSACTION_SV__

class cpu_transaction extends uvm_sequence_item;
    rand bit           CPU_RW_TYPE;//0: read, 1:write
    rand bit [16 -1:0] CPU_ADDR;
    rand bit [32 -1:0] CPU_DATA;
    rand int           cycle_post;
    
    `uvm_object_utils_begin(cpu_transaction)
        `uvm_field_int(CPU_RW_TYPE, UVM_ALL_ON)
        `uvm_field_int(CPU_ADDR, UVM_ALL_ON)
    `uvm_object_utils_end

    extern constraint cycle_post_cons;
    
    extern function new(string name = "cpu_transaction");
    extern virtual function cpu_transaction clone();
	extern virtual function void pack();
	extern virtual function void unpack();
	
endclass: cpu_transaction

constraint cpu_transaction::cycle_post_cons{
    cycle_post dist {[20:40]:/30};
}

function cpu_transaction::new(string name = "cpu_transaction");
	super.new(name);
endfunction

function cpu_transaction cpu_transaction::clone();
    cpu_transaction to = new();
    to.CPU_RW_TYPE = this.CPU_RW_TYPE;
    to.CPU_ADDR = this.CPU_ADDR;
    to.CPU_DATA = this.CPU_DATA;
    return to;
endfunction: clone

function void cpu_transaction::pack();
endfunction: pack

function void cpu_transaction::unpack();
endfunction: unpack

`endif
